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connection diagram 8-pin plastic mini-dip package rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 1 pa monolithic electrometer operational amplifier AD546* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features dc performance 1 mv max input offset voltage low offset drift: 20 m v/ 8 c 1 pa max input bias current input bias current guaranteed over full common-mode voltage range ac performance 3 v/ m s slew rate 1 mhz unity gain bandwidth low input voltage noise: 4 m v p-p, 0.1 hz to 10 hz available in a low cost, 8-pin plastic mini-dip standard op amp pinout applications electrometer amplifiers photodiode preamps ph electrode buffers log ratio amplifiers product description the AD546 is a monolithic electrometer combining the virtues of low (1 pa) input bias current with the cost effectiveness of a plastic mini-dip package. both input offset voltage and input offset voltage drift are laser trimmed, providing very high perfor- mance for such a low cost amplifier. input bias currents are reduced significantly by using topgate jfet technology. the 10 15 w common-mode impedance, resulting from a bootstrapped input stage, insures that input bias current is essentially independent of common-mode voltage variations. the AD546 is suitable for applications requiring both minimal levels of input bias current and low input offset voltage. appli- cations for the AD546 include use as a buffer amplifier for cur- rent output transducers such as photodiodes and ph probes. it may also be used as a precision integrator or as a low droop rate sample and hold amplifier. the AD546 is pin compatible with standard op amps; its plastic mini-dip package is ideal for use with automatic insertion equipment. the AD546 is available in two performance grades, all rated over the 0 c to +70 c commercial temperature range, and packaged in an 8-pin plastic mini-dip. * covered by patent no. 4,639,683. product highlights 1. the input bias current of the AD546 is specified, 100% tested and guaranteed with the device in the fully warmed-up condition. 2. the input offset voltage of the AD546 is laser trimmed to less than 1 mv (AD546k). 3. the AD546 is packaged in a standard, low cost, 8-pin mini-dip. 4. a low quiescent supply current of 700 m a minimizes any thermal effects which might degrade input bias current and input offset voltage specifications.
AD546Cspecifications (@ +25 8 c and 6 15 v dc, unless otherwise noted) rev. a C2C AD546j AD546k model conditions min typ max min typ max units input bias current 1 either input v cm = 0 v 0.2 1 0.2 0.5 pa either input v cm = 10 v 0.1 1 0.2 0.5 pa either input @ t max v cm = 0 v 40 20 pa either input v cm = 10 v 40 20 pa offset current v cm = 0 v 0.17 0.09 pa offset current @ t max v cm = 0 v 13 7 pa input offset initial offset 21 pa offset @ t max 32mv vs. temperature 20 20 m v/ c vs. supply 100 100 m v/v vs. supply t min Ct max 100 100 m v/v long-term stability 20 20 m v/month input voltage noise f = 0.1 hz to 10 hz 4 4 m v p-p f = 10 hz 90 90 nv/ ? hz f = 100 hz 60 60 nv/ ? hz f = 1 khz 35 35 nv/ ? hz f = 10 khz 35 35 nv/ ? hz input current noise f = 0.1 hz to 10 hz 1.3 1.3 fa rms f = 1 khz 0.4 0.4 fa/ ? hz input impedance differential v diff = 1 v 10 13 i 110 13 i 1 w i pf common mode v cm = 10 v 10 15 i 0.8 10 15 i 0.8 w i pf open loop gain v o = 10 v r load = 10 k w 300 1000 300 1000 v/mv t min Ct max v o = 10 v r load = 10 k w 300 800 300 800 v/mv v o = 10 v r load = 2 k w 100 250 100 250 v/mv t min Ct max v o = 10 v r load = 2 k w 80 200 80 200 v/mv input voltage range differential 3 20 20 v common-mode voltage C10 +10 C10 +10 v common-mode rejection ratio v cm = 10 v 80 90 84 100 db t min to t max 76 80 76 80 db output characteristics voltage r load = 10 k w C12 +12 C12 +12 v r load = 2 k w C10 +10 C10 +10 v current short circuit 15 20 35 15 20 35 ma load capacitance stability gain = +1 4000 4000 pf
AD546 AD546j AD546k model conditions min typ max min typ max units frequency response gain bw, small signal g = C1 0.7 1.0 0.7 1.0 mhz full power response v o = 20 v p-p 50 50 khz slew rate, unity gain g = C1 2 3 2 3 v/ m s settling time to 0.1% 4.5 4.5 m s to 0.01% 5 5 m s overload recovery 50% overdrive gain = C1 2 2 m s power supply rated performance 15 15 v operating range 6 5 6 18 6 5 6 18 v quiescent current 0.60 0.7 0.60 0.7 ma transistor count # of transistors 50 50 package options plastic mini-dip (n-8) AD546jn AD546kn notes 1 bias current specifications are guaranteed maximum, at either input, after 5 minutes of operation at t a = +25 c. bias current increases by a factor of 2.3 for every 10 c rise in temperature. 2 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = +25 c. 3 defined as max continuous voltage between inputs, such that neither exceeds 10 v from ground. specifications subject to change without notice. specifications in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. C3C rev. a absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation . . . . . . . . . . . . . . . . . . . . . . 500 mw input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v output short circuit duration . . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and Cv s storage temperature range . . . . . . . . . . . . . C65 c to +125 c operating temperature range . . . . . . . . . . . . . . 0 c to +70 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD546 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD546Ctypical characteristics (v s = 6 15 v, unless otherwise noted) supply voltage v input voltage range v 20 15 0 05 20 10 15 10 5 +v in ? in figure 1. input voltage range vs. supply voltage supply voltage v 800 700 400 05 20 10 15 600 500 quiescent current ?? figure 4. quiescent current vs. supply voltage open loop gain ?v/mv temperature ? o c 3000 1000 100 ?5 ?5 125 5356595 300 r l = 10k w figure 7. open loop gain vs. temperature supply voltage v 20 15 0 05 20 10 15 10 5 output voltage range v +25 o c r l = 10k w +v out ? out figure 2. output voltage range vs. supply voltage input common mode voltage ?v 120 common mode rejection ratio ?db 110 70 ?5 +15 ?0 0 +10 100 90 80 figure 5. cmrr vs. input common-mode voltage warm-up time ?minutes 30 0 01 7 23456 25 20 15 10 5 d |vos| v figure 8. change in offset voltage vs. warm-up time 30 15 0 100k 10k 1k 10 10 5 20 25 load resistance ? w output voltage swing ?volts p-p 100 v s = 15 volts figure 3. output voltage swing vs. resistive load r l = 10k w supply voltage v open loop gain ?v/mv 3000 1000 100 05 20 10 15 300 figure 6. open loop gain vs. supply voltage common-mode voltage ?volts 300 250 100 ?0 ? 10 05 200 150 +25 o c input bias current ?fa figure 9. input bias current vs. common-mode voltage rev. a C4C
AD546 rev. a C5C supply voltage volts 300 250 100 05 20 10 15 200 150 input bias current ?fa +25 o c figure 10. input bias current vs. supply voltage frequency ?hz open loop gain ?db 100 ?0 10 100 10m 1k 10k 100k 1m 80 60 40 0 ?0 20 phase margin ?degrees 100 ?0 80 60 40 0 ?0 20 figure 13. open loop frequency response 160 100 20 10k 1k 10 60 40 120 140 frequency ?hz 100 80 noise spectral density ?nv/ ? hz figure 11. input voltage noise spectral density vs. frequency 40 0 1m 20 5 100 15 10 35 30 100k 10k 1k frequency ?hz 10 25 output voltage swing ?v figure 14. large signal frequency response source resistance ?ohms 100k 0.1 100k 1m 100g 10m 100m 1g 10g 10k 1k 100 10 input noise voltage ?? p-p 1 whenever johnson noise is greater than amplifier noise, amplifier noise can be considered negligible for the application. resistor johnson noise 1 khz bandwidth amplifier generated noise 10 hz bandwidth figure 12. noise vs. source resistance figure 15. cmrr vs. frequency figure 16. psrr vs. frequency figure 17. output settling time vs. output swing and error voltage
AD546 rev. a C6C minimizing input current the AD546 is guaranteed to have less than 1 pa max input bias current at room temperature. careful attention to how the am- plifier is used will reduce input currents in actual applications. the amplifier operating temperature should be kept as low as possible to minimize input current. like other jfet input am- plifiers, the AD546s input current is sensitive to chip tempera- ture, rising by a factor of 2.3 for every 10 c rise. this is illustrated in figure 24, a plot of AD546 input current versus ambient temperature. figure 24. AD546 input bias current vs ambient temperature on-chip power dissipation will raise chip operating temperature causing an increase in input bias current. due to the AD546s low quiescent supply current, chip temperature when the (unloaded) amplifier is operated with 15 v supplies, is less than 3 c higher than ambient. the difference in input current is negligible. however, heavy output loads can cause a significant increase in chip temperature and a corresponding increase in input current. maintaining a minimum load resistance of 10 k w is recom- mended. input current versus additional power dissipation due to output drive current is plotted in figure 25. figure 25. AD546 input bias current vs. additional power dissipation figure 18. unity gain follower figure 21. unity gain inverter figure 20. unity gain follower small signal pulse response figure 23. unity gain inverter small signal pulse response figure 19. unity gain follower large signal pulse response figure 22. unity gain inverter large signal pulse response
AD546 rev. a C7C circuit board notes the AD546 is designed for through hole mount into pc boards. maintaining picoampere level resolution in that environment re- quires a lot of care. since both the printed circuit board and the amplifiers package have a finite resistance, the voltage differ- ence between the amplifiers input pin and other pins (or traces on the pc board) will cause parasitic currents to flow into (or out of) the signal path (see figure 26). these currents can easily exceed the 1 pa input current level of the AD546 unless special precautions are taken. two successful methods for minimizing leakage are guarding the AD546s input lines and maintaining adequate insulation resistance. the AD546s positive input (pin 3) is located next to the nega- tive supply voltage pin (pin 4). the negative input (pin 2) is next to the balance adjust pin (pin 1) which is biased at a poten- tial close to the negative supply voltage. the layouts shown in figures 27a and 27b for the inverter and follower connections will guard against the effects of low surface resistance of the board. note that the guard traces should be placed on both sides of the board. in addition the input trace should be guarded on both of its edges along its entire length. figure 26. sources of parasitic leakage currents figure 27a. guarding schemeinverter figure 27b. guarding schemefollower
AD546 rev. a C8C figure 28. input pin to insulating standoff leakage through the bulk of the circuit board will still occur with the guarding schemes shown in figures 27a and 27b. stan- dard g10 type printed circuit board material may not have high enough volume resistivity to hold leakages at the sub- picoampere level particularly under high humidity conditions. one option that eliminates all effects of board resistance is shown in figure 28. the AD546s sensitive input pin (either pin 2 when connected as an inverter, or pin 3 when connected as a follower) is bent up and soldered directly to a teflon* insu- lated standoff. both the signal input and feedback component leads must also be insulated from the circuit board by teflon standoffs or low-leakage shielded cable. contaminants such as solder flux on the boards surface and on the amplifiers package can greatly reduce the insulation resis- tance between the input pin and those traces with supply or sig- nal voltages. both the package and the board must be kept clean and dry. an effective cleaning procedure is to first swab the sur- face with high grade isopropyl alcohol, then rinse it with deion- ized water and, finally, bake it at 80 c for 1 hour. note that if either polystyrene or polypropylene capacitors are used on the printed circuit board, a baking temperature of 70 c is safer, since both of these plastic compounds begin to melt at approxi- mately +85 c. other guidelines include making the circuit layout as compact as possible and reducing the length of input lines. keeping cir- cuit board components rigid and minimizing vibration will re- duce triboelectric and piezoelectric effects. all precision high impedance circuitry requires shielding from electrical noise and interference. for example, a ground plane should be used under all high value (i.e., greater than 1 m w ) feedback resistors. in some cases, a shield placed over the resistors, or even the entire amplifier, may be needed to minimize electrical interference originating from other circuits. referring to the equation in fig- ure 26, this coupling can take place in either, or both, of two different formscoupling via time varying fields: dv dt c p or by injection of parasitic currents by changes in capacitance due to mechanical vibration: dcp dt v both proper shielding and rigid mechanical mounting of compo- nents help minimize error currents from both of these sources. table i lists various insulators and their properties. table i. insulating materials and characteristics volume minimal minimal resistance resistivity triboelectric piezoelectric to water material 1 ( v Ccm) effects effects absorption teflon* 10 17 C10 18 wwg kel-f** 10 17 C10 18 wmg sapphire 10 16 C10 18 mgg polyethylene 10 14 C10 18 mgm polystyrene 10 12 C10 18 wmm ceramic 10 12 C10 14 wmw glass epoxy 10 10 C10 17 wmw pvc 10 10 C10 15 gmg phenolic 10 5 C10 12 wgw gCgood with regard to property. mCmoderate with regard to property. wCweak with regard to property. 1 electronic measurements, pp.15-17, keithley instruments, inc., cleveland, ohio, 1977. *teflon is a registered trademark of e.i. du pont co. **kel-f is a registered trademark of 3m company. offset nulling the AD546s input offset voltage can be nulled by using balance pins 1 and 5, as shown in figure 29. nulling the input offset voltage in this fashion will introduce an added input offset volt- age drift component of 2.4 m v/ c per millivolt of nulled offset. figure 29. standard offset null circuit the circuit in figure 30 can be used when the amplifier is used as an inverter. this method introduces a small voltage in series with the amplifiers positive input terminal. the amplifiers
AD546 rev. a C9C input offset voltage drift with temperature is not affected. how- ever, variation of the power supply voltages will cause offset shifts. figure 30. alternate offset null circuit for inverter ac response with high value source and feedback resistance source and feedback resistances greater than 100 k w will magnify the effect of input capacitances (stray and inherent to the AD546) on the ac behavior of the circuit. the effects of common-mode and differential-input capacitances should be taken into account since the circuits bandwidth and stability can be adversely affected. in a follower, the source resistance, r s , and input common- mode capacitance, c s (including capacitance due to board and capacitance inherent to the AD546), form a pole that limits cir- cuit bandwidth to 1/2 p r s c s . figure 31 shows the follower pulse response from a 1 m w source resistance with the amplifiers input pin isolated from the board, only the effect of the AD546s input common-mode capacitance is seen. figure 31. follower pulse response from 1 m w source resistance in an inverting configuration, the differential input capacitance forms a pole in the circuits loop transmission. this can create peaking in the ac response and possible instability. a feedback capacitance can be used to stabilize the circuit. the inverter pulse response with r f and r s equal to 1 m w , and the input pin isolated from the board appears in figure 32. figure 33 shows the response of the same circuit with a 1 pf feedback capaci- tance. typical differential input capacitance for the AD546 is 1 pf. figure 32. inverter pulse response with 1 m w source and feedback resistance figure 33. inverter pulse response with 1 m w source and feedback resistance, 1 pf feedback capacitance common-mode input voltage overload the rated common-mode input voltage range of the AD546 is from 3 v less than the positive supply voltage to 5 v greater than the negative supply voltage. exceeding this range will de- grade the amplifiers cmrr. driving the common-mode volt- age above the positive supply will cause the amplifiers output to saturate at the upper limit of output voltage. recovery time is typically 2 m s after the input has been returned to within the normal operating range. driving the input common mode volt- age within 1 v of the negative supply causes phase reversal of the output signal. in this case, normal operation is typically resumed within 0.5 ms of the input voltage returning within range. differential input voltage overload a plot of the AD546s input current versus differential input voltage (defined as v in + Cv in C) appears in figure 34. the figure 34. input current vs. differential input voltage
AD546 rev. a C10C input current at either terminal stays below a few hundred femtoamps until one input terminal is forced higher than 1 v to 1.5 v above the other terminal. under these conditions, the input current limits at 30 m a. input protection the AD546 safely handles any input voltage within the supply voltage range. subjecting the input terminals to voltages beyond the power supply can destroy the device or cause shifts in input current or offset voltage if the amplifier is not protected. a protection scheme for the amplifier as an inverter is shown in figure 35. the protection resistor, r p , is chosen to limit the current through the inverting input to 1 ma for expected tran- sient (less than 1 second) overvoltage conditions, or to 100 m a for a continuous overload. since r p is inside the feedback loop, and is much lower in value than the amplifiers input resistance, it does not affect the inverters dc gain. however, the johnson noise of the resistor will add root sum of squares to the amplifiers input noise. figure 35. inverter with input current limit in the corresponding version of this scheme for a follower, shown in figure 36, r p and the capacitance at the positive input terminal will produce a pole in the signal frequency response at a f = 1/2 p rc. again, the johnson noise of r p will add to the amplifiers input voltage noise. figure 37 is a schematic of the AD546 as an inverter with an in- put voltage clamp. bootstrapping the clamp diodes at the invert- ing input minimizes the voltage across the clamps and keeps the leakage due to the diodes low. low leakage diodes (less figure 36. follower with input current limit figure 37. input voltage clamp with diodes than 1 pa), such as the fd333s should be used, and should be shielded from light to keep photocurrents from being generated. even with these precautions, the diodes will measurably increase the input current and capacitance. in order to achieve the low input bias currents of the AD546, it is not possible to use the same on-chip protection as used in other analog devices op amps. this makes the AD546 sensitive to handling and precautions should be taken to minimize esd exposure whenever possible. figure 38. sample and difference circuit for measuring electrometer leakage currents measuring electrometer leakage currents there are a number of methods used to test electrometer leak- age currents, including current integration and direct current to voltage conversion. regardless of the method used, board and interconnect cleanliness, proper choice of insulating materials (such as teflon or kel-f), correct guarding and shielding tech- niques and care in physical layout are essential for making accu- rate leakage measurements. figure 38 is a schematic of the sample and difference circuit which is useful for measuring the leakage currents of the AD546 and other electrometer amplifiers. the circuit uses two ad549 electrometer amplifiers (a and b) as current to voltage convert- ers with high value (10 10 w ) sense resistors (rsa and rsb). r1 and r2 provide for an overall circuit sensitivity of 10 fa/mv (10 pa full scale). c c and c f provide noise suppression and loop compensation. c c should be a low leakage polystyrene ca- pacitor. an ultralow-leakage kel-f test socket is used for con-
AD546 rev. a C11C tacting the device under test. rigid teflon coaxial cable is used to make connections to all high impedance nodes. the use of rigid coax affords immunity to error induced by mechanical vi- bration and provides an outer conductor for shielding. the en- tire circuit is enclosed in a grounded metal box. the test apparatus is calibrated without a device under test present. a five minute stabilization period after the power is turned on is required. first, v err1 and v err2 are measured. these voltages are the errors caused by offset voltages and leak- age currents of the current to voltage converters. v err 1 = 10 ( v os a C i b a rsa ) v err 2 = 10 ( v os b C i b b rsb ) once measured, these errors are subtracted from the readings taken with a device under test present. amplifier b closes the feedback loop to the device under test, in addition to providing current to voltage conversion. the offset error of the device un- der test appears as a common-mode signal and does not affect the test measurement. as a result, only the leakage current of the device under test is measured. v a C v err 1 = 10[ rsa i b (+)] v x C v err 2 = 10[ rsb i b (C)] although a series of devices can be tested after only one calibra- tion measurement, calibration should be updated periodically to compensate for any thermal drift of the current-to-voltage con- verters or changes in the ambient environment. laboratory re- sults have shown that repeatable measurements within 10 fa can be realized when this apparatus is properly implemented. these results are achieved in part by the design of the circuit, which eliminates relays and other parasitic leakage paths in the high impedance signal lines, and in part by the inherent cancellation of errors through the calibration and measurement procedure. photodiode interface the AD546s 1 pa current and low input offset voltage make it a good choice for very sensitive photodiode preamps (figure 39). the photodiode develops a signal current, i s , equal to: i s = r p where p is light power incident on the diodes surface in watts and r is the photodiode responsivity in amps/watt. r f converts the signal current to an output voltage: v out = r f i s figure 39. photodiode preamp dc error sources and an equivalent circuit for a small area (0.2 mm square) photodiode are indicated in figure 40. input current, i b , will contribute an output voltage error, v e1 , proportional to the feedback resistance: v e 1 = i b r f the op amps input voltage offset will cause an error current through the photodiodes shunt resistance, r s : i = v os / r s the error current will result in an error voltage (v e2 ) at the amplifiers output equal to: v e 2 = (1 + r f / r s ) v os given typical values of photodiode shunt resistance (on the or- der of 10 9 w ), r f /r s can be greater than one, especially if a large feedback resistance is used. also, r f /r s will increase with tem- perature, as photodiode shunt resistance typically drops by a factor of two for every 10 c rise in temperature. an op amp with low offset voltage and low drift helps maintain accuracy. figure 40. photodiode preamp dc error sources photodiode preamp noise noise limits the signal resolution obtainable with the preamp. the output voltage noise divided by the feedback resistance is the minimum current signal that can be detected. this mini- mum detectable current divided by the responsivity of the pho- todiode represents the lowest light power that can be detected by the preamp. noise sources associated with the photodiode, amplifier, and feedback resistance are shown in figure 41; figure 42 is the voltage spectral density versus frequency plot of each of the noise sources contribution to the output voltage noise (circuit parameters in figure 40 are assumed). each noise sources rms contribution to the total output voltage noise is obtained by in- tegrating the square of its spectral density function over fre- quency. the rms value of the output voltage noise is the square root of the sum of all contributions. minimizing the total area under these curves will optimize the preamplifiers resolution for a given bandwidth. figure 41. photodiode preamp noise sources
AD546 rev. a C12C printed in u.s.a. c1291C10C7/89 figure 42. photodiode preamp noise sources spectral density vs. frequency the photodiode preamp in figure 39 can detect a signal current of 26 fa rms at a bandwidth of 16 hz, which assuming a photo- diode responsivity of 0.5 a/w, translates to a 52 fw rms mini- mum detectable power. the photodiode used has a high source resistance and low junction capacitance. c f sets the signal band- width with r f and also limits the peak in the noise gain that multiplies the op amps input voltage noise contribution. a single pole filter at the amplifiers output limits the op amps output voltage noise bandwidth to 26 hz, a frequency compa- rable to the signal bandwidth. this greatly improves the preamplifiers signal to noise ratio (in this case, by a factor of three). photodiode array processor the AD546 is a cost effective preamp for multichannel applica- tions, such as amplifying signals from photo diode arrays, as il- lustrated in figure 43. an AD546 preamp converts each of the diodes output currents to a voltage. an 8 to 1 multiplexer switches a particular preamp output to the input of an ad1380 16-bit sampling adc. the output of the adc can be displayed or put onto a databus. additional preamps and muxes can be added to handle larger arrays. layout of multichannel circuits is critical. refer to pc board notes for guidance. ph probe amplifier a ph probe can be modeled as a mv-level voltage source with a series source resistance dependent upon the electrodes compo- sition and configuration. the glass bulb resistance of a typical ph electrode pair falls between 10 6 w and 10 9 w . it is, therefore, important to select an amplifier with low enough input currents such that the voltage drop produced by the amplifiers input bias current and the electrode resistance does not become an appreciable percentage of a ph unit. the circuit in figure 44 illustrates the use of the AD546 as a ph probe amplifier. as with other electrometer applications, the use of guarding, shielding, teflon standoffs, etc., is a must in order to capitalize on the AD546s low input current. if an AD546j (1 pa max input current) is used, the error contributed by input current will be held below 10 mv for ph electrode source impedances up to 10 9 w . input offset voltage (which can be trimmed) will be below 2 mv. refer to ad549 data sheet for temperature compensated ph probe amplifier circuit. figure 43. photodiode array processor figure 44. ph probe amplifier outline dimensions dimensions shown in inches and (mm). mini-dip (n) package

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